Programmable logic systems, as well as other circuit designs, are often created with the help of Computer Aided Design (CAD) tools. Typically, a designer creates a Hardware Description Language (HDL) design file, sometimes called a Verilog HDL file, with instructions for the circuit functionality. The CAD tool creates a circuit description after several steps that can be described at a high level as synthesis, place & route, timing analysis, and simulation. The result is a binary file with instructions for programming and configuration of the programmable logic system. An example of a commercially available CAD tool is QUARTUS™ II available from the assignee.
During synthesis, the HDL chip description is translated into a basic discrete netlist of logic-gate primitives followed by the optimization of the basic netlist. Synthesis uses a series of algorithms that minimize the number of technology cells and optimize the signal speed through the technology cell paths. Many different synthesis algorithms are available, but the synthesis tool design engineer must often discard some of these algorithms because of long processing time requirements or because they are only useful in a small percentage of circuits. Runtime is an important factor when selecting algorithms because circuit designers are hampered by short time constraints. This tradeoff between quality and runtime must be considered when selecting the algorithms to be used during synthesis.
In addition to requiring long runtimes or lacking utility for most circuits, many available beneficial synthesis algorithms are discarded because they take a long time to detect the circuit type, or because there is not enough information in the HDL source code to determine with certainty the type of circuit. If the synthesis tool had information on the type of circuit desired, it would be possible to use circuit-specific synthesis algorithms that provide substantial improvements with low runtime overhead.
In some circuit designs, the CAD will detect timing problems that may render a programmable device not useful for an intended purpose, such as for supporting Input/Output (I/O) operations at desired speeds. If the programmable device has been binned at a lower speed than the actual speed supported by the device, the programmable device may still be able to support such operations if the timing analysis could be fine tuned.
Therefore, there is a need to quickly identify circuit types in HDL code so the synthesis process can eliminate circuit identification processing as well as take advantage of more efficient algorithms, resulting in improved circuit area, circuit speed, and design tool runtime. Additionally, there is a need to better control timing analysis for programmable devices.